This invention relates to data processing systems.
The performance of data processing units is improving at a rate greater than that of main memory (RAM) storage. The latencies involved in memory access are typically several times the average execution time of an instruction and can thus degrade performance dramatically. On the other hand, the latencies are not usually long enough to make it worth while switching to execute a different process while the memory is being accessed.
The effect of memory latency on processor performance can be reduced by reducing the number of main memory accesses, for example by using a large, possibly multi-level cache. However, for some types of application it is almost impossible to reduce the cache miss rate to less than 5%-10% and in such cases memory access time can still dominate the overall processor performance. For example, large database applications typically exhibit random access profiles to records which may be distributed within gigabytes of memory and in such a case the cache miss rate can be very high.
The object of the present invention is to provide a novel data processing system architecture which overcomes or alleviates these problems.